Materials for CHREC 2008 Midyear Workshop

Workshop materials are provided below in PDF form and also (in case animation is featured) in PPT form. Access to presentation materials is restricted to CHREC members and sites. Members should please contact one of the CHREC faculty or staff members for the access code.

Note: in project designations, F = University of Florida, G = George Washington University, B = Brigham Young University, and V = Virginia Tech.

Individual presentations are included below. The full proceedings is available in one file (293 slides) here: [PDF (11MB)] [PPT (33MB)]

Session I: General Topics

• Welcome & Greetings, NSF Update Briefing, State of the Center [PDF] [PPT]

FDTE Concepts
• F1-08: System-Level Formulation for Algorithm/Architecture Exploration [PDF] [PPT]
• V1-08: Model-Based Engineering Framework for HPRC Applications [PDF] [PPT]
• F2-08: Application Performance Analysis [PDF] [PPT]
• G6-08: Intelligent Deployment of IP Cores [PDF] [PPT]

Fault Tolerance
• F4-08: Reconfigurable Fault Tolerance and Partial Reconfiguration [PDF] [PPT]
• B3-08: High-Reliability RC Design Tools and Techniques [PDF] [PPT]
• B4-08: Reliable RC DSP/Comm Systems [PDF] [PPT]

Session III: Project Reviews -- Part B

Device Studies
• F5-08: Device Characterization & Design Space Exploration [PDF] [PPT]
• B2-08: Heterogeneous Architectures for HPEC RC [PDF] [PPT]
• V2-08: Process-to-Core Mapping for Advanced Architectures [PDF] [PPT]
• G7-08: Partial Run-Time Reconfiguration for HPRC [PDF] [PPT]

Application Studies & Core Libraries
• F3-08: Case Studies in Multi-FPGA Application Design [PDF] [PPT]
• G5-08: Library Portability for HLL Acceleration Cores [PDF] [PPT]
• B1-08: Core Library Framework for HPC/HPEC [PDF] [PPT]

• List of posters [PDF]

• Link to NSF on-line entry site for LIFE forms (password provided by Jena @ workshop)

• Study for DARPA by BYU and VT (now part of CHREC) [PDF] [PPT]
• Study for DARPA by CHREC (c/o founding sites) [PDF] [PPT]

• Workshop Agenda
• Travel Info